Please use this identifier to cite or link to this item: http://hdl.handle.net/2289/7803
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dc.contributor.authorT, Prabu-
dc.contributor.authorB, Stappers-
dc.contributor.authorA, Ghalame-
dc.contributor.authorL, Levin-
dc.contributor.authorA, Karastergiou-
dc.contributor.authorJ, Roy-
dc.contributor.authorM, Mickaliger-
dc.contributor.authorM, Keith-
dc.date.accessioned2021-07-27T06:14:02Z-
dc.date.available2021-07-27T06:14:02Z-
dc.date.issued2020-09-
dc.identifier.citation33rd General Assembly and Scientific Symposium of the International-Union-of-Radio-Scienceen_US
dc.identifier.urihttp://hdl.handle.net/2289/7803-
dc.descriptionRestricted Accessen_US
dc.description.abstractThis paper presents a design which uses an FPGA (Field Programmable Gate Array) to search for radio pulsars in binary systems for the Square Kilometre Array (SKA). The search pipeline executes Doppler de-acceleration algorithm in real-time to identify binary pulsar spin periods. It involves a very large computation and the algorithm implementation for a real-time execution with power efficiency for the SKA is a challenging task. The design follows a Fourier domain acceleration search method, which is essentially a matched filtering technique, where the complex spectra of the dedispersed time-series are convolved with a set of Doppler demodulation templates. Convolution outputs are systematically summed over a number of harmonics and signatures of periodic signals are detected and passed on for subsequent downstream processing. This design is developed for modern FPGA technology and a prototype of the design is implemented and tested on a commercial FPGA accelerator platform. Salient details of the work are presented in the paper.en_US
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rights2020 IEEEen_US
dc.titleFPGA architecture to search for accelerated pulsars with SKAen_US
dc.typeArticleen_US
Appears in Collections:Research Papers(EEG)

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