Offset, Gain and Phase Calibration of Quad ADC EV10AQ190

Abstract

Due to technological limitations, commercial ADCs having multi-gigahertz sampling bandwidth and high bit precision (≥ 6 bits) are not easily available. For wide bandwidth applications, one option to enhance the sampled bandwidth is to time-interleave multiple ADC cores within a package. In an ideal scenario, parameters like DC offset, gain, phase and bandwidth of individual ADC cores within a package are identical. However, due to variations in the ADC manufacturing processes, the above parameters may not be identical in all ADC cores. Modern time-interleaved ADCs provide programmable features to calibrate these parameters so as to obtain optimal spurious-free dynamic-range performance.