Offset, Gain and Phase Calibration of Quad ADC EV10AQ190

Please use this identifier to cite or link to this item: http://hdl.handle.net/2289/7850

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DC Field	Value	Language
dc.contributor.author	S, Madhavi	-
dc.contributor.author	B.S., Girish	-
dc.contributor.author	K.S., Srivani	-
dc.date.accessioned	2021-12-14T06:40:51Z	-
dc.date.available	2021-12-14T06:40:51Z	-
dc.date.issued	2017-04-06	-
dc.identifier.citation	RRI-EEG Internal Technical Report No.: 2017/01	en_US
dc.identifier.uri	http://hdl.handle.net/2289/7850	-
dc.description	Restricted Access	en_US
dc.description.abstract	Due to technological limitations, commercial ADCs having multi-gigahertz sampling bandwidth and high bit precision (≥ 6 bits) are not easily available. For wide bandwidth applications, one option to enhance the sampled bandwidth is to time-interleave multiple ADC cores within a package. In an ideal scenario, parameters like DC offset, gain, phase and bandwidth of individual ADC cores within a package are identical. However, due to variations in the ADC manufacturing processes, the above parameters may not be identical in all ADC cores. Modern time-interleaved ADCs provide programmable features to calibrate these parameters so as to obtain optimal spurious-free dynamic-range performance.	en_US
dc.language.iso	en	en_US
dc.publisher	Raman Research Institute, Bengaluru	en_US
dc.rights	2017 Raman Research Institute, Bengaluru	en_US
dc.subject	Class: Digital Receiver	en_US
dc.title	Offset, Gain and Phase Calibration of Quad ADC EV10AQ190	en_US
dc.type	Technical Report	en_US
Appears in Collections:	Technical Reports (EEG)

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OGP_Cal_ver1_06Apr2017.pdf	Restricted Access	1.23 MB	Adobe PDF	View/Open